ARM has fingers

http://infocenter.arm.com/help/topic/com.arm.doc.dui0489c/Cjabicci.html

The IT (If-Then) instruction makes up to four following instructions (the IT block) conditional. The conditions can be all the same, or some of them can be the logical inverse of the others.

LOL. I don't think even the VAX had one of those.

That doesn't sound very RISCy.

>>2
They've got less money than Intel does, so they have to play it safe.

>>2
ARM never was very RISCy. It only appears that way when placed alongside older architectures that predate it. Every instruction on the original ARM could be predicated.

>>4
RISC doesn't imply "only the most basic commands". It just implies a reduced-sized instruction set as compared to CISC.

This is how ARM can stay competitive to x86, and why MIPS and the rest are ridiculously far behind.

They've done far more CISCy things though:
http://en.wikipedia.org/wiki/Jazelle

>>5
Classical RISC design means exactly that, actually. Look at the original MIPS design if you don't believe me.

>>7
But ARM is the Advanced RISC Machine, not Classical RISC Machine. No one wants the CRM because RISC purists take it to far and you end up with a Turing tarpit stack machine with ten instructions.

``RISC'' is a marketing buzzword.

>>9
Wrong! It's actually a marketing buzzacronym.

>>10

implying acronym is not a word

>>11
E^P_IC

>>11
Yes, I'm implying precisely that. What're you going to do about it?

>>13
*grabs dick*

>>14
But I haven't washed. Enjoy your stinky hands.

>>15
Oh, I will.

>>8,10
The A in ARM will always stand for Acorn as far as I'm concerned. (Didn't ARM Holdings drop "RISC" from their name too, just because some barbarian in marketing was afraid it would spook investors? They have no credibility there, I'm afraid.)

I'd dip in Turing's Tarpit if you know what I mean.

>>1
I just understood the pun in your title, OP.

>>18
Reimu's ARMpit is superior.

>>1
ARM assembly guru here. They removed conditional execution from the newer AArch64 (aka ARM64) architecture. It was becoming more of a nuisance with the introduction of deeper pipelines, instruction parallelism, and instruction reordering--it can be done, but it requires a combinatorial explosion of gates the deeper the pipeline gets.

With ARM being on the small form-factor, low-power consumption part of the spectrum, it made sense to drop it.

>>21
Just removing an instruction in the name of practicallity. Absolutely humiliating. Intel would not only support that instruction, but would devote ten million more transistors to supporting it at every stage of the 37(ish?) stage pipeline. This is why MIPS should have won the RISC wars.

>>20
http://danbooru.donmai.us/posts/699543

>>22
Humiliating? Depends how you look at it. ARM processors dominate the mobile market, precisely because of the pragmatism that ARM engineers have had over the years. Intel is the one that is feeling humiliated for not being able to really break into the mobile market.

Not that any of us here really care about mobile though. Mobile is for normies.

AArch64 does double the general purpose register count to 32, with a dedicated zero register. They also double the 128-bit NEON SIMD registers, and add double-precision support. They have dedicated instructions and processing units for AES encrypt/decrypt and SHA-1/SHA-2.

Nothing revolutionary like what Intel's doing with their recent processors though. The ADX arbitrary-precision integer arithmetic extensions Intel recently added, for example.

>>24
ADX isn't revolutionary. TSX, on the other hand...

>>24

Humiliating

Pretty sure >>22 was a joke.