Hardware Design of x86

computers throw interrupt when you divide by 0 instead of returning NaN/Inf/MaxInt
Instructions left from early 80's
shift and rotates with more than 1 cycle latency
privilege rings
task segments

RISC-V does not cause exceptions on arithmetic errors, including overflow, underflow, subnormal and divide by zero. Instead, both integer and floating-point arithmetic produce reasonable default values and set status bits. Divide-by-zero can be discovered by a single branch after the division. The status bits can be tested by an operating system or periodic interrupt.[3]