risc v based arduinething

Pretty good you can actually bie it now. Really hardware with a RISC v chip you can progrqm. I like it.

I WANT TO
 BELIEVE

Wherefore art thou, Romeo?

>>3 Romeo became MGTOW, leaving the whores and bitches to Chads.
Checkmate atheists.

JACKSON FIVE GET

https://www.crowdsupply.com/sifive/hifive1/

The one thing lacking in the E310 is analog support, but this just puts the chip in the same ballpark as the majority of microcontrollers that only provide digital peripherals. Off-chip analog peripheral chips are available and often utilized where higher accuracy or performance is needed.

>>1,6
Do you know if there's any design intended for accelerated 3D graphics processing? It would be fantastic to get a chip like the FE310 and an open GPU into a EOMA68 computer.

I don't know too much about CPU design but it seems this RISC-V thing as a whole isn't very thought through:
- 32 regs for the standard version, 16 for the low spec. Wouldn't it have made sense to have 16 regs in the standard ver and 32 in a 'luxury' version? I've heard the jump from 8 to 16 for x86_64 hadn't much of a positive effect, so why would an increase from 16 to 32? Then again, this is a load/store-machine...
- Support for multiple float widths. Isn't 32 bit precision basically a waste of effort due to precision issues? Wouldn't a width of at least 64 bits make sense?
- Couldn't they have taken the clue from DLX/MIPS and optimize code density somehow? RISC-V instructions are variable in size anyway, so why not opt for, say, a 16 bit instruction size? Remember that cache still is one of the largest issues today, so making the code maybe ~10% smaller is already a big win. It seems like they took the worst of two worlds (decoding complexity AND inefficient cache use) and put them together...

Also take note that this crowdfunding thingy doesn't have float support. Just so you know. But hey, at least it has multicore support for its single CPU.

>>9
32 registers is fairly popular for risc cpus, same number that avr and mips have. These chips have much slower memory than a desktop and a much smaller amount of it, and often have to work in hard real-time environments, so having lots of registers makes sense.

also, 8 registers on x86 was a huge bottleneck for optimization, the increase to 16 on amd64 has been nothing but good from benchmarks I've seen.

Don't know about the other points.

>>11
checked

check em

>>11
sweet dubs