VHDL

entity OriginalLogic is
port (A,B,C,D: in bit; X out bit);
end entity OriginalLogic;
architecture Expression1 of OriginalLogic is
begin
X <= not ((A and c) or not (b and not c) or D) or not (not (B and C));
end architecture Expression1;

>>4
it is, it's a double negation