Brain-damaged academics with no appreciation of reality, as usual...
Compiled code only used a few CISC instructions anyways[sic]
That's because compilers are, as I've already mentioned here countless times, still
absolutely fucking retarded when it comes to good instruction selection. RISC is an equally retarded architecture, trying to make it impossible for a human to beat a compiler because it's so dumbed down that there's no way to generate better code. Instead of making compilers better, they're making everyone else worse to make themselves look better in comparison.
Enable pipelined implementations
That's not a RISC advantage since the P6's uop decoding.
CISC executes fewer instructions per program (~3/4X instructions)
...more like "an arbitrary amount less" for things like REP MOVS/STOS/CMPS.
99% Processors today are RISC
Quality != quantity. Shitty MIPS is everywhere in stuff you don't even know about.
Widely agreed (still) that RISC principles are best for general-purpose ISA
Absolute Bullshit. Maybe only among the RISC circlejerkers.
Security
Scaremongering authoritarian freedom-haters.
What if there were free and open ISAs we could use for everything?
386/486. Pentium patents are expiring soon if they haven't already.
Curious lack of any mention of the horrible instruction density and the memory bandwidth bottleneck in those slides... really makes you wonder how deluded these fucktards are.
I've said it before and I'll say it again: CISC can always get faster by moving microcoded instructions into dedicated hardware. Good luck trying to "decompile" a series of RISC instructions back into an operation that can be performed on dedicated hardware when it becomes available like a multiplier, divider, AES round, etc.