entity OriginalLogic is port (A,B,C,D: in bit; X out bit); end entity OriginalLogic; architecture Expression1 of OriginalLogic is begin X <= not ((A and c) or not (b and not c) or D) or not (not (B and C)); end architecture Expression1;
Name:
Anonymous2018-02-28 16:25
VHDL may be case insensitive, but it's still sloppy coding.
The basic module that is used to describe a design in VHDL is known as the design entity. The design entity consists of two units - interfaces and bodies. In addition, VHDL also has other design units - functions, and packages. These are described as follows.
● Interface: The interface describes the external characteristics of the design, especially information about input and output ports. The interface can also be used to describe generic parameters, such as the timing characteristics (e.g., 30 ns delay), fanout, and size of a digital compoenent. A number of declarations and assertions about the ports (in or out) and the types (binary or integer) they handlecan also be specified by the interface. The interface of a 4-bit serial adder and a single constituent full adder (FA) are given below.
Example 1: VHDL Interface for 4-bit adder
entity FOUR_ADDER
- port (X, Y: in BIT BIT_VECTOR (3..0); Cin: in BIT - carry input Cout: out BIT - carry output SUM: out BIT_VECTOR(3..0)) is - output sum - parameter generic (DELAY: time : = 30 NS); assertion DELAY > 5ns;
end FOURBIT_ADDER;
EXAMPLE 2: VHDL Interface for a FA
entity FULL_ADDER
-ports (Cin, X, Y: in BIT; Cout, SUM: out BIT)
end FULL_ADDER
Name:
Anonymous2018-03-07 8:34
● Body: The body describes a possible implementation (out of many) of a design. For instance, this description could be architectural, or behavioral. Structural information is encapsulated in the architectural description, while control flow descriptions can be embodied within the behavioral description. The behavioral description of a 4-bit serial adder is shown below, along with an architectural description of the body of a single full adder (FA). Example 3 describes one possible behavioral description, ADD4, of a 4-bit adder, FOURBIT_ADDER. Example 4 describes the architectural body of a single of Full Adder. The statements of a behavioral body are executed sequentially, while those of an architectural body are executed in parallel.
Example 3: VHDL behavioral Body of 4-bit adder.
behavioral body ADD4 of FOURBIT_ADDER is
variable t, tx, ty: hexsum - temporary variables
begin tx : = inte(X); - X converted to integer from binary ty : = inte (Y): - Y converted to integer from binary t : = tx + ty; - sum calculated Cout & SUM < = bin(t) after DELAY; converted from integer to binary.
end ADD4
Example 4: VHDL architectural Body of a FA.
architectural body GATE_LEVEL-STRUCTURE of FULL_ADDER is component AND_GATE(X,Y: in BIT; C: out BIT); component XOR_GATE(X,Y: in BIT; C: out BIT); component OR_GATE(X,Y: in BIT; C: out BIT); signal S1, S2, S3: BIT;