RISC-V is bloated crapshit

https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

It has variable instruction (wtf) and on the base architecture only it supports 11 different types of instruction encoding. I would not be surprised if it used half of the instruction length just selecting what the encoding is.

Why not just make mips cpus instead?

What always triggered me about MIPS was the wasted bits for the unused shift amount field, which they could have easily aliased to the third register field (and introducing a new shift-arith-only instruction type), or introduce fused shift instructions like in ARM.
Well, they fixed that now.
By replacing it with a third (!) opcode field. 17 (7+3+7) of 32 bits needed to differentiate between an ADD and a MUL.

Then you think: well, okay, what should they have done with those 5 ``useless'' bits instead?

They should have made MIPS a variable length encoding of 16 bit wide instruction words from the very start instead of a 32 bit fixed width encoding.