RISC-V is bloated crapshit

https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

It has variable instruction (wtf) and on the base architecture only it supports 11 different types of instruction encoding. I would not be surprised if it used half of the instruction length just selecting what the encoding is.

Why not just make mips cpus instead?

MIPS? Loongson shill detected.

What always triggered me about MIPS was the wasted bits for the unused shift amount field, which they could have easily aliased to the third register field (and introducing a new shift-arith-only instruction type), or introduce fused shift instructions like in ARM.
Well, they fixed that now.
By replacing it with a third (!) opcode field. 17 (7+3+7) of 32 bits needed to differentiate between an ADD and a MUL.

Then you think: well, okay, what should they have done with those 5 ``useless'' bits instead?

They should have made MIPS a variable length encoding of 16 bit wide instruction words from the very start instead of a 32 bit fixed width encoding.

ARM is the future. x86 is a sinking ship. RISC/SPARC/MIPS are useless.

>>2
Still waiting, Lemote.

>>5
oh geez I remember this faggot

>>3
But muh instruction decode complexity! John Hennessy told me this is bad; why would he lie?

>>7
I'm no HW designer so this *might* be a thing.
However, RISC-V seems to have variable instruction size, anyway (don't quote me on that).

Also, they tested (simulated?) a 16b encoding, that could work together with standard 32b instructions (when aligned)¹.
Outcome: it's likely to be more energy efficient and faster².

1980s HW design: no idea.
1995+ HW design: cache usage > a lot of other things.

¹https://en.wikipedia.org/wiki/RISC-V#The_compressed_set
²https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-63.html

On a system with a 16 KB direct-mapped instruction cache and 32 KB 2-way data cache, 9% of all main memory accesses (instruction and data) are eliminated, performance is 4% better, and 25% fewer instruction bits need be fetched.