RISC-V is bloated crapshit

https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

It has variable instruction (wtf) and on the base architecture only it supports 11 different types of instruction encoding. I would not be surprised if it used half of the instruction length just selecting what the encoding is.

Why not just make mips cpus instead?

>>3
But muh instruction decode complexity! John Hennessy told me this is bad; why would he lie?